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[Other] sdramcontol

Description: SDRAM的 详细构造,工作原理,控制说明-SDRAM detailed structure, working principle, control description
Platform: | Size: 859136 | Author: li ji wei | Hits:

[VHDL-FPGA-Verilog] an499_design_example

Description: cpld 控制 8-32M sdram 控制器 maxII epm570实现。-CPLD control 8-32M sdram controller maxII epm570 realize.
Platform: | Size: 433152 | Author: 王可见 | Hits:

[VHDL-FPGA-Verilog] AlteraSdramIP

Description: Altera Sdram IP 源码，VHDL写的-Altera Sdram IP source code, VHDL written
Platform: | Size: 781312 | Author: 张敏 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: vhdl 编写的sdram controler, 双通道-VHDL prepared sdram controler, dual-channel
Platform: | Size: 3072 | Author: chenchungen | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_verilog

Description: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Platform: | Size: 752640 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: DE2开发板提供的四端口SDRAM驱动，用户不需要对SDRAM直接操作，把SDRAM对用户透明化-DE2 development board provides four-port SDRAM drive, users do not need to direct the operation of the SDRAM, the SDRAM transparent to users
Platform: | Size: 15360 | Author: 旺仔 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Platform: | Size: 1021952 | Author: shroy | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Platform: | Size: 776192 | Author: 费尔德 | Hits:

[Windows Develop] Sun86

Description: SDRAM仿真文件，主要用于测试SDRAM的控制程序是否正确。-SDRAM simulation files, mainly used for testing control procedures SDRAM is correct.
Platform: | Size: 1078272 | Author: weigaozu | Hits:

[VHDL-FPGA-Verilog] SDRAM_simulation_model

Description: sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
Platform: | Size: 93184 | Author: 朱宝军 | Hits:

[VHDL-FPGA-Verilog] sdram_design

Description: SDRAM存取控制器设计书，包含标准的SDRAM读写控制功能，和自动刷新功能。对VHDL设计初学者很有帮助。密码MMCTEAM。-SDRAM access controller design books, contain standard SDRAM read and write control functions, and auto refresh function. VHDL design helpful for beginners. Password MMCTEAM.
Platform: | Size: 243712 | Author: John | Hits:

[VHDL-FPGA-Verilog] sdram_ver_134

Description: SDRAM控制器的源代码打包下载，不错不错值得-SDRAM controller source code pack download, well worth a good try
Platform: | Size: 115712 | Author: jinyong | Hits:

[VHDL-FPGA-Verilog] sdram_hr_hw

Description: 在FPGA硬件上实现计算机通过串口发数据给FPGA，数据保存到SDRAM中，然后又返回给计算机串口。-In FPGA hardware realize computer data through the serial port issued to FPGA, the data saved to SDRAM, and then again back to the computer serial port.
Platform: | Size: 5217280 | Author: huanghui | Hits:

[VHDL-FPGA-Verilog] ddr2sdram_spartan3s700an.tar

Description: It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit- Diligent fully working.
Platform: | Size: 1488896 | Author: under | Hits:

[VHDL-FPGA-Verilog] vga_core(vhdl)

Description: vga视频输出（vhdl），主要是从sdram中产生图形，输出到vga中-vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
Platform: | Size: 459776 | Author: 程荣 | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_vhd

Description: SDR SDRAM的VHDL描述，比较详细，还有数据手册-SDR SDRAM the VHDL description, more detailed, have data sheet
Platform: | Size: 717824 | Author: 顾康 | Hits:

[VHDL-FPGA-Verilog] sdramctrl

Description: sdram controller vhdl
Platform: | Size: 15360 | Author: wangxiaolong | Hits:

[VHDL-FPGA-Verilog] sdramctrl2

Description: sdram controller 2 vhdl
Platform: | Size: 15360 | Author: wangxiaolong | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl1

Description: FPGA读写SDRAM的VHDL程序，已经测试过-FPGA to read and write the VHDL procedures SDRAM have been tested
Platform: | Size: 5120 | Author: 钟灿武 | Hits:
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